Floating gate nitridation

ABSTRACT

The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to integrated circuits, and moreparticularly to nonvolatile integrated memories.

[0002]FIG. 1 shows a cross section of a stacked gate nonvolatile memorycell such as used in flash and non-flash electrically erasableprogrammable read only memories (EEPROM). Conductive floating gate 110,made of doped polysilicon, overlies monocrystalline silicon substrate120. Silicon dioxide 130 insulates the floating gate from the substrate.N type source/drain regions 140 in substrate 120 are separated by P typechannel region 150. Channel region 150 is directly below the floatinggate. Dielectric 160 separates the floating gate from control gate 170made of doped polysilicon.

[0003] The memory cell is read by applying a voltage between the regions140, applying a voltage between one of the regions 140 and control gate170, and detecting a current through the other one of the regions 140.The memory cell is written (programmed or erased) by modifying a chargeon floating gate 110. Floating gate 110 is completely insulated on allsides. The modify the charge on the floating gate, electrons aretransferred between the floating gate and substrate 150 through oxide130. The electrons can be transferred by Fowler-Nordheim tunneling orhot electron injection. See “Nonvolatile Semiconductor MemoryTechnology” (1998) edited by W. D. Brown and J. E. Brewer, pages 10-25,incorporated herein by reference. The electron transfer requires avoltage to be established between the floating gate and a substrateregion (the substrate region can be channel 150 or a source/drain region140). This voltage is established by creating a voltage between thesubstrate region and the control gate. The control gate voltage iscoupled to the floating gate. To reduce the voltage required to becreated between the substrate region and the control gate, a highcapacitive coupling is needed between the floating and control gates. Ahigh specific capacitance (capacitance per unit area) can be obtainedbetween the floating and control gates by reducing the thickness ofdielectric 160. However, dielectric 160 functions as a barrier to acharge leakage from the floating gate to the control gate. Therefore,dielectric 160 has to be a high quality, thin, uniform dielectric inorder to provide good data retention (low leakage) and ensure apredictable high capacitive coupling between the floating and controlgates.

[0004] Dielectric 160 can be silicon dioxide. Also, ONO (silicondioxide, silicon nitride, silicon dioxide) has been used. See U.S. Pat.No. 4,613,956 issued Sep. 23, 1986 to Peterson et al. Another option isa combination of silicon dioxide and oxynitride layers. Thus, accordingto U.S. Pat. No. 6,274,902, a silicon dioxide layer is thermally grownon floating gate polysilicon, and an oxynitride layer is deposited byLPCVD (low pressure chemical vapor deposition) on the silicon dioxide.

SUMMARY

[0005] This section summarizes some features of the invention. Theinvention is defined by the appended claims that are incorporated intothis section by reference.

[0006] In some embodiments of the present invention, before thedielectric 160 is formed, the top surface of floating gate 110 isnitrided to incorporate nitrogen atoms. The nitridation may involve ionimplantation of pure nitrogen or nitrogen compounds into layer 110.Alternatively, the nitridation can be accomplished by exposing thesurface of layer 110 to a nitrogen containing plasma. Other techniques,known or to be invented, are also possible.

[0007] After the nitridation process, silicon dioxide is thermally grownon the nitrided surface of layer 110. The nitrogen atoms in layer 110slow down the oxidation process, so a more uniform silicon dioxide layerwith fewer defects can be formed. Optionally, other dielectric layers(e.g. silicon nitride, silicon dioxide, oxynitride) are formed on thethermally grown silicon dioxide layer.

[0008] In some embodiments, dielectric 160 includes a top layer ofsilicon dioxide. The top silicon dioxide layer is nitrided toincorporate nitrogen atoms. The nitrogen atoms may be pure nitrogen orpart of nitrogen compounds. The nitrogen atoms reduce the leakagecurrent, thus improving the data retention. Some of the nitrogen maybind with silicon atoms of the silicon oxide layer to form siliconnitride. The silicon nitride has a higher dielectric constant thansilicon dioxide, thus increasing the capacitive coupling between thefloating and control gates.

[0009] Some embodiments combine the features described above, i.e. thenitridation of floating gate 110 and the nitridation of the top silicondioxide surface of dielectric 160.

[0010] The invention is applicable to split gate memories and otherflash and non-flash floating gate memories, known or to be invented.Other features of the invention are described below. The invention isdefined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 shows a cross section of a prior art nonvolatile memorycell.

[0012] FIGS. 2-7 show cross sections of nonvolatile memory cells in theprocess of fabrication according to some embodiments of the presentinvention.

DESCRIPTION OF SOME EMBODIMENTS

[0013]FIG. 2 illustrates a cross section of a nonvolatile memory cell atan early stage of fabrication. Semiconductor substrate 120(monocrystalline silicon or some other material) is processed to form asuitably doped channel region 150 (type P in FIG. 2, but an N typechannel can also be used). Dielectric 130 is formed on substrate 120over channel 150. Dielectric 130 may be thermally grown silicon dioxideor some other type of dielectric. Then polysilicon layer 110 isdeposited and doped during or after deposition. See for example U.S.patent application Ser. No. 09/640,139 filed Aug. 15, 2000 andincorporated herein by reference.

[0014] The top surface of polysilicon 110 is nitrided to incorporatenitrogen atoms. The nitrogen atoms may be pure nitrogen or part ofnitrogen compounds. In one embodiment, nitrogen is implanted by ionimplantation to a doze of 10¹³ to 10¹⁵ atoms/cm² at an energy 1-30 keV.Optionally, the structure is thermally annealed. In one embodiment, theanneal is performed at 850-1000° C. for 10 to 60 seconds.

[0015] In another embodiment, nitridation is performed with plasma. Forexample, remote plasma nitridation (RPN) can be used. RPN involvesexposing the layer 110 to high density nitrogen plasma generated outsideof a chamber containing the wafer. See U.S. Pat. No. 6,268,296 and U.S.patent publication 20010021588, both incorporated herein by reference.

[0016] In one embodiment, RPN is performed in a system of type Centura®available from Applied Materials, Inc. of Santa Clara, Calif. Suitableprocess parameters are: Wafer temperature 300-500° C. Pressure  1-100torr Nitrogen (N₂) 0.5 slm (standard liters per minute) to 5 slm Helium(He)  1-6 slm Time  10-600 seconds

[0017] Other parameters can also be used.

[0018] Optionally, a thermal anneal is conducted. For example, thestructure can be held at 900-1100° C. at a pressure of 1 to 500 torr inthe atmosphere of any of N₂, He, NO, O₂, N₂O, or a combination of thesesgases. An exemplary anneal time is 10-150 seconds.

[0019] Another suitable plasma nitridation process is decoupled plasmanitridation (DPN) performed in a machine of type Gate Stack™ Centura®available from Applied Materials, Inc. of Santa Clara, Calif. A similarmachine, a Decoupled Plasma Source of type Centura®, is described inU.S. Pat. No. 6,074,954 issued on Jun. 13, 2000 to Lill et al. andincorporated herein by reference. Exemplary process parameters are:Power on the coil outside 100-500 W the processing chamber Pressure 10mTorr to 10 Torr N₂ flow 50 sccm to 2 slm Time  10-100 seconds

[0020] Optionally, the structure is annealed. The anneal parametersdescribed above for the RPN process are suitable.

[0021] After the nitridation step, the exemplary surface concentrationof nitrogen atoms is 1-20 atomic percent in some embodiments. Theexemplary thickness of the nitrided layer 110.1 at the top of layer 110is below 3 nm. These parameters are not limiting.

[0022] As shown in FIG. 2, the nitridation can be performed before thelayer 110 is patterned. Alternatively, the nitridation can be performedafter this layer is patterned. The nitridation can be a blanket process,or a mask can be used to block nitrogen from some wafer regions. In thefloating gate regions, both silicon and nitrogen atoms are present atthe top surface of layer 110.

[0023] Then silicon dioxide 310 (FIG. 3) is formed by thermal oxidationor chemical vapor deposition (CVD) on the nitrided surface of layer 110.Thermal oxidation can be performed at 800-1050° C. in an oxygen oroxygen/hydrogen atmosphere. In some embodiments, the thermal oxidegrowth rate is up to 10 times less than for a non-nitrided siliconsurface. An exemplary thickness of layer 310 is 3 to 8 nm. Otherthicknesses, processes, and process parameters may also be used. FIG. 3shows the layer 310 to be on top of nitrided layer 110.1. In fact, someor all of the silicon atoms in layer 110.1 can be consumed by theoxidation process. A layer of silicon dioxide with Si_(x)N_(y) moleculescan form as a result.

[0024] Known techniques can be used to complete the memory fabrication.In the example of FIG. 4, silicon nitride layer 410 is formed by lowpressure CVD (LPCVD) on layer 310. Silicon dioxide 420 is deposited byCVD, or thermally grown, on layer 410. Layers 310, 410, 420 arereferenced as 160. Doped polysilicon 170, or some other conductivematerial, is deposited to provide the control gates (possibly wordlineseach of which provides the control gates for a row of memory cells). Thelayers 170, 420, 410, 310, 110, 130 are patterned as needed.Source/drain regions 140 are formed by doping. Additional layers (notshown) may be formed to provide select gates, erase gates, or otherfeatures. See the aforementioned U.S. patent application Ser. No.09/640,139 for an exemplary memory fabrication process that can bemodified to incorporate the floating gate nitridation described above.

[0025] In FIG. 5, the nitridation of floating gate polysilicon 110 isomitted. Silicon dioxide 310 is formed on polysilicon 110 usingconventional techniques (e.g. thermal oxidation or CVD). Then siliconnitride 410 is deposited. Silicon dioxide 420 is deposited by CVD orgrown thermally on nitride 410. An exemplary thickness of layer 420 is3-8 nm. Layers 310, 410 can be omitted or replaced with other dielectriclayers.

[0026] The top surface of oxide 420 is nitrided to improve the dataretention. The capacitance is also increased as nitrogen binds withsilicon to form silicon nitride. The nitridation can be performed, forexample, by ion implantation, RPN or DPN, using the processes describedabove for nitridation of polysilicon 110. A thermal anneal can beperformed at the end of the nitridation as described above for layer110.

[0027] In some embodiments, the surface concentration of nitrogen atomsis 1-20 atomic percent, and the thickness of the nitrided layer 420.1 atthe top of layer 420 is below 3 nm.

[0028] Conductive layer 170 (FIG. 6), for example, doped polysilicon, isformed on the nitrided surface of oxide 420 as described above inconnection with FIG. 4. This layer will provide the control gate. Thestructure is patterned and the fabrication is completed as describedabove in connection with FIG. 5.

[0029] In FIG. 7, the techniques of FIGS. 2-6 are combined. Floatinggate polysilicon 110 is nitrided as described above in connection withFIG. 2. Then one or more dielectric layers are deposited (e.g. oxide310, nitride 410, and oxide 420), with the top layer being silicondioxide. The top silicon dioxide layer 420 is nitrided as describedabove in connection with FIG. 5. Then conductive layer 170 is formed andthe fabrication is completed as described above.

[0030] Nitridation of floating gate polysilicon 110 and/or silicondioxide 420 does not lead to a significant change in the total physicalthickness of dielectric 160. However, the specific capacitance betweenthe floating and control gates increases by 5 to 20% in some embodimentsdepending on the nitridation conditions. Other capacitance parameterscan also be obtained.

[0031] The memory cells of FIGS. 4, 6, 7 can be operated like the memorycell of FIG. 1. The memory can be programmed by Fowler-Nordheimtunneling of electrons from channel 150 or source/drain region 140 tofloating gate 110. The memory can be erased by Fowler-Nordheim tunnelingof electrons from the floating gate to channel 150 or a source/drainregion 140. In other embodiments, the memory is programmed by hotelectron injection, and erased by Fowler-Nordheim tunneling. In stillother embodiments, the memory is erased by tunneling of electrons fromthe floating gate to a separate erase gate (not shown). Other memorystructures, including split gate structures with select gates, and otherprogramming and erase mechanisms, known or to be invented, can also beused.

[0032] The invention is not limited to the embodiments described above.The invention is not limited to the particular nitridation techniques orprocess parameters, layer thicknesses, or other details. The inventionis not limited to the particular shape of the floating and control gatesor their positioning relative to each other. The invention is notlimited to particular materials. For example, polysilicon 110 can bereplaced with amorphous silicon, monocrystalline silicon, or theircombinations. Silicon dioxide (SO₂) can be replaced, or mixed with,silicon monoxide (we will use the term “silicon oxide” to refer both tosilicon dioxide and silicon monoxide). Other embodiments and variationsare within the scope of the invention, as defined by the appendedclaims.

1. A method for manufacturing an integrated circuit comprising anonvolatile memory, the method comprising: forming a first layercomprising silicon, the first layer being to provide one or morefloating gates for the nonvolatile memory; nitriding a surface of thefirst layer to incorporate nitrogen atoms into said surface; forming afirst dielectric at the nitrided surface, wherein forming the firstdielectric comprises forming silicon oxide at the nitrided surface;forming a conductive layer separated from the nitrided surface by thefirst dielectric, the conductive layer providing one or more controlgates for the nonvolatile memory.
 2. The method of claim 1 whereinforming the silicon oxide at the nitrided surface comprises forming thesilicon oxide by thermal oxidation.
 3. The method of claim 1 wherein thesurface of the first layer is a polysilicon surface.
 4. An integratedcircuit manufactured by the method of claim
 1. 5. An integrated circuitcomprising a nonvolatile memory cell: a channel region; a firstdielectric on a surface of the channel region; a conductive floatinggate on the first dielectric, the floating gate having a surface whichhas silicon and nitrogen atoms therein; silicon oxide formed at saidsurface of the floating gate; a conductive control gate opposite to saidsurface of the floating gate.
 6. The integrated circuit of claim 5further comprising a second dielectric between said surface of thefloating gate and the control gate.
 7. A method for manufacturing anintegrated circuit comprising a nonvolatile memory, the methodcomprising: forming a first layer to provide one or more floating gatesfor the nonvolatile memory; forming a first dielectric on a surface ofthe first layer, wherein the first dielectric comprises a first surfacecomprising silicon oxide; nitriding the first surface of the firstdielectric to incorporate nitrogen atoms into the first surface; forminga conductive layer on the nitrided first surface of the firstdielectric, the conductive layer providing one or more control gates forthe nonvolatile memory.
 8. An integrated circuit manufactured by themethod of claim
 7. 9. An integrated circuit comprising a nonvolatilememory cell comprising: a channel region; a first dielectric on asurface of the channel region; a conductive floating gate on the firstdielectric; a second dielectric on a surface of the floating gate; and aconductive control gate separated from the floating gate by the seconddielectric; wherein the second dielectric comprises a layer of siliconoxide having a surface having nitrogen atoms embedded therein; and thecontrol gate contacts said silicon oxide surface with nitrogen atoms.